Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism

One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors

In this paper, we employ a newly-developed one-dimensional multi-subband Monte Carlo (1DMSMC) simulation module to study electron transport in nanowire structures. The 1DMSMC simulation module is integrated into the GSS TCAD simulator GARAND coupling a MC electron trajectory simulation with a 3D Poisson-2D Schrödinger solver, and accounting for the modified acoustic phonon, optical phonon, and surface roughness scattering mechanisms. We apply the simulator to investigate the effect of the overlap factor, scattering mechanisms, material and geometrical properties on the mobility in silicon nanowire field-effect transistors (NWTs). This paper emphasizes the importance of using 1D models that include correctly quantum confinement and allow for a reliable prediction of the performance of NWTs at the scaling limits. Our simulator is a valuable tool for providing optimal designs for ultra-scaled NWTs, in terms of performance and reliability

Impact of Strain on the Performance of Si Nanowires Transistors at the Scaling Limit: A 3D Monte Carlo/2D Poisson Schrodinger Simulation Study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs

Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

Metamorphosis of a nano wire: A 3-D coupled mode space NEGF study

In this paper we present a 3D coupled mode space NEGF study of the quantum features of a nanoscale Gate-All- Around (GAA) silicon transistor. The bottom oxide of the structure is parameterized in order to progressively transform the nanowire in a tri-gate FinFET and the electron transport studied for several Fin widths, back-biases voltages and electron effective masses. Moreover, we address in detail the treatment of the boundary conditions at the channel interface to model the wave function penetration into the gate oxide. We report quantitative results of the charge density obtained by a simplified and a complete discretization approach

Simulation study of the impact of quantum confinement on the electrostatically driven oerformance of n-type nanowire transistors

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions

Multi-Subband Ensemble Monte Carlo simulation of Si nanowire MOSFETs

The need for an accurate simulation of non-planar devices such as FinFETs and nanowire based FETs, including a full quantun treatment of transversal two-dimensional confinement, motivated the development of a three-dimensional MultiSubband Ensemble Monte Carlo (MS-EMC) simulator. Here we describe the last improvements of such simulator including better convergence properties and statistical improvements for the computation of the drain current. The simulator is employed to study MOS devices based on Si nanowires with lateral sizes of a few nanometers. The results show the importance of a proper two-dimensional treatment of quantum confinement, which can be achieved with our simulator